View AD9945KCPZRL7_8074349.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad9945 complete 12-bit 40 mhz ccd signal processor features 40 msps correlated double sampler (cds) 6 db to 40 db 10-bit variable gain amplifier (vga) low noise optical black clamp circuit preblanking function 12-bit 40 msps a/d converter no missing codes guaranteed 3-wire serial digital interface 3 v single-supply operation low power: 140 mw @ 3 v supply space-saving 32-lead 5 mm 5 mm lfcsp applications digital still cameras digital video camcorders pc cameras portable ccd imaging devices cctv cameras functional block diagram dataclk shd shp band gap reference dout ccdin pblk reft refb internal timing 6db to 40db avdd dvdd dvss avss drvdd drvss 10 digital interface sdata sck sl clpob 12 ad9945 control registers 12-bit adc clp vga cds general description the ad9945 is a complete analog signal processor for ccd applications. it features a 40 mhz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area ccd arrays. the ad9945? signal chain consists of a correlated double sampler (cds), a digitally con- trolled variable gain amplifier (vga), a black level clamp, and a 12-bit a/d converter. the internal registers are programmed through a 3-wire serial digital interface. programmable features include gain adjustment, black level adjustment, input clock polarity, and power-down modes. the ad9945 operates from a single 3 v power supply, typi- cally d issipates 140 mw, and is packaged in a space-saving 32-lead lfcsp.
rev. a ? ad9945?pecifications general specifications parameter min typ max unit temperature range operating ?0 +85 c storage ?5 +150 c power supply voltage analog, digital, digital driver 2.7 3.6 v power consumption normal operation (drvdd power not included) 140 mw drvdd power only (c load = 20 pf) 10 mw power-down mode 1.5 mw maximum clock rate 40 mhz specifications subject to change without notice. digital specifications parameter symbol min typ max unit logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs high level output voltage, i oh = 2 ma v oh 2.2 v low level output voltage, i ol = 2 ma v ol 0.5 v specifications subject to change without notice. (drvdd = dvdd = 2.7 v, c l = 20 pf, unless otherwise noted.) (t min to t max , avdd = dvdd = drvdd= 3.0 v, f samp = 40 mhz, unless otherwise noted.)
rev. a ad9945 ? parameter min typ max unit notes cds maximum input range before saturation * 1.0 vp-p allowable ccd reset transient * 500 mv see input waveform in footnote maximum ccd black pixel amplitude * 100 mv variable gain amplifier (vga) gain control resolution 1024 steps gain monotonicity guaranteed gain range minimum gain 5.3 db see figure 7 for vga gain curve maximum gain 40.0 41.5 db see variable gain amplifier section for vga gain equation black level clamp clamp level resolution 256 steps clamp level measured at adc output minimum clamp level 0 lsb maximum clamp level 255 lsb a/d converter resolution 12 bits differential nonlinearity (dnl) 0.5 lsb no missing codes guaranteed data output coding straight binary full-scale input voltage 2.0 v voltage reference reference top voltage (reft) 2.0 v reference bottom voltage (refb) 1.0 v system performance specifications include entire signal chain gain range low gain (vga code = 0) 5.3 db maximum gain (vga code = 1023) 40.0 41.5 db gain accuracy 1.0 db peak nonlinearity, 500 mv input signal 0.1 % 12 db gain applied total output noise 1.2 lsb rms ac grounded input, 6 db gain applied power supply rejection (psr) 40 db * input signal characteristics defined as follows: 500mv typ reset transient 100mv typ optical black pixel 1v typ input signal range specifications subject to change without notice. system specifications (t min to t max , avdd = dvdd = drvdd = 3.0 v, f samp = 40 mhz, unless otherwise noted.)
rev. a ? ad9945 timing specifications parameter symbol min typ max unit sample clocks dataclk, shp, shd clock period t conv 25 ns dataclk high/low pulse width t adc 10 12.5 ns shp pulse width t shp 6.25 ns shd pulse width t shd 6.25 ns clpob pulse width * t cob 220 pi xels shp rising edge to shd falling edge t s1 6.25 ns shp rising edge to shd rising edge t s2 11.25 12.5 ns internal clock delay t id 3ns data outputs output delay t od 9.5 ns pipeline delay 10 cycles serial interface maximum sck frequency f sclk 10 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge setup t ds 10 ns sck falling edge to sdata valid hold t dh 10 ns * minimum clpob pulse width is for functional operation only. wider typical pulses are recommended to achieve low noise clamp per formance. specifications subject to change without notice. (c l = 20 pf, f samp = 40 mhz, ccd mode timing in figures 8 and 9, serial timing in figures 4 and 5.) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9945 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * with respect parameter to min max unit avdd avss ?.3 +3.9 v dvdd dvss ?.3 +3.9 v drvdd drvss ?.3 +3.9 v digital outputs drvss ?.3 drvdd + 0.3 v s hp, shd, dataclk dvss ?.3 dvdd + 0.3 v clpob, pblk dvss ?.3 dvdd + 0.3 v sck, sl, sdata dvss ?.3 dvdd + 0.3 v reft, refb, ccdin avss ?.3 a vdd + 0.3 v junction temperature 150 c lead temperature 300 c (10 sec) * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. ordering guide temperature package package model range description 1 option ad9945kcp ?0 c to +85 c lfcsp cp-32 ad9945kcprl ?0 c to +85 c lfcsp cp-32 ad9945kcprl7 ?0 c to +85 c lfcsp cp-32 ad9945kcpz 2 ?0 c to +85 c lfcsp cp-32 AD9945KCPZRL7 2 ?0 c to +85 c lfcsp cp-32 1 lfcsp = lead frame chip scale package 2 z = pb-free part. thermal characteristics thermal resistance 32-lead lfcsp package ja = 27.7 c/w
rev. a ad9945 ? pin configuration top view 24 refb 23 reft 22 ccdin 21 avss d2 1 d3 2 d4 3 32 d1 20 avdd 19 shd 18 shp 17 clpob d10 9 d11 10 drvdd 11 drvss 12 dvdd 13 dataclk 14 dvss 15 pblk 16 d5 4 d6 5 d7 6 d8 7 d9 8 31 d0 30 nc 29 nc 28 nc 27 sck 26 sdata 25 sl ad9945 pin 1 indicator pin function descriptions pin number mnemonic type description 1 to 10, 31, 32 d2 to d11, d0, d1 do digital data outputs 11 drvdd p digital output driver supply 12 drvss p digital output driver ground 13 dvdd p digital supply 14 dataclk di digital data output latch clock 15 dvss p digital supply ground 16 pblk di preblanking clock input 17 clpob di black level clamp clock input 18 shp di cds sampling clock for ccd? reference level 19 shd di cds sampling clock for ccd? data level 20 avdd p analog supply 21 avss p analog ground 22 ccdin ai analog input for ccd signal 23 reft ao a/d converter top reference voltage decoupling 24 refb ao a/d converter bottom reference voltage decoupling 25 sl di serial digital interface load pulse 26 sdata di serial digital interface data input 27 sck di serial digital interface clock input 28 to 30 nc nc internally pulled down. float or connect to gnd. type: ai = analog input, ao = analog output, di = digital input, do = digital output, p = power.
rev. a ? ad9945 equivalent input circuits 330 dvdd dvss figure 1. digital inputs?hp, shd, dataclk, clpob, pblk, sck, sl, sdata dvdd dvss drvss drvdd three- state data dout figure 2. data outputs?0 to d11 60 avdd a vss a vss figure 3. ccdin (pin 22) definitions of specifications differential nonlinearity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. thus, every code must have a finite width. no missing codes guaranteed to 12-bit resolution indicates that all 4096 codes must be present over all operating conditions. peak nonlinearity peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the ad9945 from a true straight line. the point used as zero scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular output code to the true straight line. the error is then expressed as a percentage of the 2 v adc full- scale signal. the input signal is always appropriately gained up to fill the adc? full-scale range. total output noise the rms output noise is measured using histogram techniques. the standard deviation of the adc output codes is calculated in lsb and represents the rms noise level of the total signal chain at the specified gain setting. the output noise can be converted to an equivalent voltage, using the relationship 1 lsb = (adc full scale/ 2 n codes) where n is the bit resolution of the adc. for the ad9945, 1 lsb is 0.5 mv. power supply rejection (psr) the psr is measured with a step change applied to the supply pins. this represents a very high frequency disturbance on the ad9945? power supply. the psr specification is calculated from the change in the data outputs for a given step change in the supply voltage. internal delay for shp/shd the internal delay (also called aperture delay) is the delay that occurs from the time when a sampling edge is applied to the ad9945 until the actual sample of the input signal is held. both shp and shd sample the input signal during the transition from low to high, so the internal delay is measured from each clock? rising edge to the instant the actual internal sample is taken.
rev. a t ypical performance characteristics?d9945 ? sample rate (mhz) 180 105 40 32 power dissipation (mv) 25 150 165 135 120 90 v dd = 3.3 v v dd = 3.0 v v dd = 2.7 v tpc 1. power vs. sampling rate 0 4000 1600 800 2400 3200 code dnl (lsb) 1.0 0.5 0 ? 0.5 ? 1.0 tpc 2. typical dnl performance
rev. a ? ad9945 internal register description table i. internal register map register address bits name a2 a1 a0 data bits function operation 0 0 0 d0 software reset (0 = normal operation, 1 = reset all registers to default) d2, d1 power-down modes (00 = normal power, 01 = standby, 10 = total shutdown) d3 ob clamp disable (0 = clamp on, 1 = clamp off) d5, d4 test mode. should always be set to 00. d6 pblk blanking level (0 = blank output to zero, 1 = blank to ob clamp level) d8, d7 test mode 1. should always be set to 00. d11 to d9 test mode 2. should always be set to 000. control 0 0 1 d0 shp/shd input polarity (0 = active low, 1 = active high) d1 dataclk input polarity (0 = active low, 1 = active high) d2 clpob input polarity (0 = active low, 1 = active high) d3 pblk input polarity (0 = active low, 1 = active high) d4 three-state data outputs (0 = outputs active, 1 = outputs three-stated) d5 data output latching (0 = latched by dataclk, 1 = latch is transparent) d6 data output coding (0 = binary output, 1 = gray code output) d11 to d7 test mode. should always be set to 00000. clamp level 0 1 0 d7 to d0 ob clamp level (0 = 0 lsb, 255 = 255 lsb) vga gain 0 1 1 d9 to d0 vga gain (0 = 6 db, 1023 = 40 db) note: all register values default to 0x000 at power-up except clamp level, which defaults to 128 decimal (128 lsb clamp level).
rev. a ad9945 ? serial interface sdata sck sl test bit a2 0 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 t ds t dh t ls t lh notes 1. sdata bits are internally latched on the rising edges of sck. 2. system update of loaded registers occurs on sl rising edge. 3. all 12 data bits d0 to d11 must be written. if the register contains fewer than 12 bits, zeros should be used for the undefined bits. 4. test bit is for internal use only. must be set low. d11 figure 4. serial write operation sdata a0 a1 a2 d0 d1 d2 d3 d4 d5 d10 d11 sck sl 0 notes 1. multiple sequential registers may be loaded continuously. 2. the first (lowest address) register address is written, followed by multiple 12-bit data-words. 3. the address will automatically increment with each 12-bit data-word (all 12 bits must be written). 4. sl is held low until the last desired register has been loaded. 5. new data is updated at the next sl rising edge. d0 d1 d10 d11 d0 ... ... ... data for starting register address data for next register address d2 d1 ... ... ... ... ... ... 1 16 2345678910 15 18 17 28 27 30 29 31 test bit figure 5. continuous serial write operation to all registers
rev. a ?0 ad9945 circuit description and operation the ad9945 signal processing chain is shown in figure 6. each processing step is essential in achieving a high quality image from the raw ccd pixel data. dc restore to reduce the large dc offset of the ccd output signal, a dc restore circuit is used with an external 0.1 f series coupling capacitor. this restores the dc level of the ccd signal to approximately 1.5 v to be compatible with the 3 v single supply of the ad9945. correlated double sampler the cds circuit samples each ccd pixel twice to extract the video information and reject low frequency noise. the timing shown in figure 8 illustrates how the two cds clocks, shp and shd, are used to sample the reference level and data level of the ccd signal, respectively. the ccd signal is sampled on the rising edges of shp and shd. placement of these two clock signals is critical in achieving the best performance from the ccd. an internal shp/shd delay (t id ) of 3 ns is caused by internal propagation delays. optical black clamp the optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the ccd? black level. during the optical black (shielded) pixel interval on each line, the adc output is compared with the fixed black level reference, selected by the user in the clamp level register. the resulting error signal is filtered to reduce noise, and the correction value is applied to the adc input through a d/a converter. normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. if external digital clamping is used during the postprocessing, the ad9945 optical black clamping may be disabled using bit d3 in the operation register (see the serial interface timing and internal register description sections). when the loop is disabled, the clamp level register may still be used to provide programmable offset adjustment. horizontal timing is shown in figure 9. the clpob pulse should be placed during the ccd? optical black pixels. it is recom- mended that the clpob pulse be used during valid ccd dark pixels. the clpob pulse should be a minimum of 20 pixels wide to minimize clamp noise. shorter pulse widths may be used, but clamp noise may increase and the loop? ability to track low fre- quency variations in the black level will be reduced. a/d converter the adc uses a 2 v input range. better noise performance results from using a larger adc full-scale range. the adc uses a pipe lined architecture with a 2 v full-scale input for low noise performance. variable gain amplifier the vga stage provides a gain range of 6 db to 40 db, program- mable w ith 10-bit resolution through the serial digital interface. the minimum gain of 6 db is needed to match a 1 v input signal with the adc full-scale range of 2 v. a plot of the vga gain curve is shown in figure 7. vga gain db vga code db db () = () + 0 035 5 3 .. vga gain register code 42 0 vga gain (db) 127 255 383 511 639 767 895 1023 36 30 24 18 12 6 figure 7. vga gain curve 6db to 40db ccdin digital filtering clpob dc restore optical black clamp dout 12-bit adc vga 8-bit dac clamp level register 8 vga gain register 10 cds internal v ref 2v full scale 12 0.1 f figure 6. ccd mode block diagram
rev. a ad9945 ?1 ccd mode timing nn+1n+2 n +9 n+10 t id t id t s1 t od n?10 n? 9 n? 8 n? 1 n notes 1. re commended placement for dataclk rising edge is between the shd rising edge and next shp falling edge. 2. ccd signal is sampled at shp and shd rising edges. shp shd dataclk output data ccd signal t s2 t cp figure 8. ccd mode timing ccd signal effective pixels clpob optical bl ack pixels horizontal blanking dummy pixels effective pixels pblk notes 1. clpob will overwrite pblk. pblk will not affect clamp operation if overlapping with clpob. 2. pblk signal is optional. 3. digital output data will be all zeros during pblk. output data latency is nine dataclk cycles. output data effective pixel data ob pixel data dummy black effective data figure 9. typical ccd mode line clamp timing
rev. a ?2 ad9945 applications information the ad9945 is a complete analog front end (afe) product for digital still camera and camcorder applications. as shown in figure 10, the ccd image (pixel) data is buffered and sent to the ad9945 analog input through a series input capacitor. the ad9945 performs the dc restoration, cds, gain adjustment, black level correction, and analog-to-digital conversion. the ad9945s digital output data is then processed by the image processing asic. the internal registers of the ad9945?sed to control gain, offset level, and other functions?re programmed by the asic or microprocessor through a 3-wire serial digital interface. a system timing generator provides the clock signals for both the ccd and the afe. ccd ccdin bu ffer v out ad9945 adc out register- data serial interface digital outputs digital image processing asic timing generator v-drive ccd timing cds/clamp timing 0.1 f figure 10. system applications diagram
rev. a ad9945 ?3 internal power-on reset circuitry after power-on, the ad9945 will automatically reset all internal registers and perform internal calibration procedures. this takes approximately 1 ms to complete. during this time, normal clock signals and serial write operations may occur. however, serial register writes will be ignored until the internal reset operation is completed. grounding and decoupling recommendations as shown in figure 11, a single ground plane is recommended for the ad9945. this ground plane should be as continuous as possible. this will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. all decoupling capacitors should be located as close as possible to the package pins. a single clean power supply is recommended for the ad9945, but a separate digital driver supply may be used for drvdd (pin 11). drvdd should always be decoupled to drvss (pin 12), which should be connected to the analog ground plane. advan- tages of using a separate digital driver supply include using a lower voltage (2.7 v) to match levels with a 2.7 v asic, reducing digital power dissipation, and reducing potential noise coupling. if the digital outputs (pins 1 to 10, 31, and 32) must drive a load larger than 20 pf, buffering is recommended to reduce digital code transition noise. alternatively, placing series resis- tors close to the digital output pins may also help reduce noise. 24 refb 23 reft 22 ccdin 21 avss d2 1 d3 2 d4 3 32 20 avdd 19 shd 18 shp 17 clpob d5 4 d6 5 d7 6 d8 7 d9 8 31 30 nc 29 nc 28 nc 27 sck 26 sdata 25 sl data outputs 12 d10 d11 9 10 3v driver supply drvdd drvss dvdd dataclk dvss pblk 12 13 14 15 16 3v analog supply 5 clock inputs 3 serial interface 3v analog supply ccdin pin 1 identifier ad9945 (not to scale) top view 1.0 f 0.1 f 0.1 f 0.1 f 0.1 f d0 d1 nc = no connect 11 1.0 f note the exposed pad on the bottom of the ad9945 should be soldered to the gnd plane of the printed circuit board figure 11. recommended circuit configuration for ccd mode
rev. a ?4 ad9945 outline dimensions 32-lead lead frame chip scale package (lfcsp) 5 mm 5 mm body (cp-32) dimensions shown in millimeters compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 nom 0.05 max 0.02 nom 12 max 1.00 0.90 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 bottom view 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq sq 3.25 3.10 2.95 pin 1 indicator 0.60 max 0.60 max
rev. a ad9945 ?5 revision history location page 11/03?ata sheet changed from rev. 0 to rev. a changes to timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
c03636??1/03(a) ?6

▲Up To Search▲

Price & Availability of AD9945KCPZRL7

	To Download AD9945KCPZRL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .